Mallaiah A, Swamy GN and Padmapriya K
In computerized PCs number of arithmetic operations, the comparator is the vital equipment unit, composed of CMOS innovation. Another procedure named as Quantum Cellular Automata (QCA) will supplant the CMOS outlines, having leverage concerning zone, control utilization, and latency. The primary QCA circuits planned with the inverter and majority voter entryways. In this paper, we utilize the clocking method 180º out of phase clock hybrid to outline the 1-bit comparator and contrast and the current outcomes. The new proposed wire crossing plan lessens the quantity of cells required to configuration, power and area necessities. Besides, we planned 2-bit comparator with 11 number of majority voters, 2 number of crossovers with 0.38 um^2 area, 203 number of cells. The designed 1-bit comparator contrast and the past outcomes where cells, region, defer demonstrates 53.57%, 50%, 33.32% improvement respectively.
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